# Writing Makefiles ## Pattern rules In prerequesite, use exactly one `%`. Can then be used in requirements. E.g. %.o: %.c # compile .c file to .o Details: ## Automatic variables * `$@`: current target * `$<`: first prerequisite * `$^`: all prerequisites, separated by spaces * `$*`: target without extension * `$(@F)`: file-within-directory part of target path More: ## C-related flags * `CC`: C compiler * `CFLAGS`: flags for `CC` * `LDFLAGS`: flags for the linker ## Text functions * `$(var:suffix=replacement)`, syntax sugar for `$(patsubst %suffix, $replacement, $(var))` More: ## Filename functions ## Recipes * `@`: don't print command ran * `-`: don't exit on command failure ## Arguments * `-B, --always-make`: force to make all targets