# Writing Makefiles ## Pattern rules In prerequesite, use exactly one `%`. Can then be used in requirements. E.g. %.o: %.c # compile .c file to .o Details: ## Automatic variables * `$@`: current target * `$<`: first prerequisite * `$^`: all prerequisites, separated by spaces * `$(@F)`: file-within-directory part of target path More: ## Text functions * `$(var:suffix=replacement)`, syntax sugar for `$(patsubst %suffix, $replacement, $(var))` More: ## Filename functions ## Quiet commands By default, `make` prints the command being run. Prepend `@` to silence this.